1. Field of the Invention
The present patent relates to a block switch of a flash memory device, and more specifically, to a block switch of a flash memory device in which a high voltage can be output stably even at a low power supply voltage and the operating time can be reduced while not increasing the chip area.
2. Discussion of Related Art
FIG. 1 is a circuit diagram showing the configuration of a conventional NAND-type flash memory device. The NAND-type flash memory device includes a plurality of cell blocks 100 and row decoders 200.
One of the cell blocks 100 includes a plurality of cell strings 110 to which a plurality of cells is serially connected, the m number of bit lines BL, the n number of word lines WL, drain select transistors 120 connected between the cell strings 110 and the bit lines BL, and source select transistors 130 connected between the cell strings 110 and a common source line. Meanwhile, a plurality of memory cells that share on word line constitute one page 140. All the cells share a P well. Furthermore, the drain select transistors 120 share a drain select line DSL and the source select transistors 130 share a source select line SSL.
One of the row decoders 200 includes a predecoder 210, a block select circuit 220 and a plurality of path transistors 230. The predecoder 210 decides a bias of a plurality of global word lines GWL0 to GWLn-1 in order to perform a given operation, and supplies operation of high voltage through the plurality of the global word lines GWL0 to GWLn-1. For example, the predecoder 210 supplies a select voltage through one of the global word lines GWL0 to GWLn-1 and a non-select voltage through another of the global word lines GWL0 to GWLn-1 in order to perform the given operation.
The block select circuit 220 includes a plurality of block switches 240 corresponding to the number of the cell blocks 100. The block switches 240 of a selected block operate to output a block select signal Bsel. The block select signal Bsel turns on the path transistors 230 of a selected cell block and turns off the path transistors 230 of a non-selected block. In this time, the block switches 240 generate the block select signals Bsel, which is higher than a voltage received through the global word lines GWL0 to GWLn-1, so as to transfer a voltage received from the predecoder 210 through the global word lines GWL0 to GWLn-1 stably. Accordingly, the selected cell block is supplied with the select voltage (Vsel) or the non-select voltage (Vunsel) through the plurality of the global word lines GWL0 to GWLn-1, the plurality of the path transistors 230 and the word lines WL0 to WLn-1. Meanwhile, the non-selected cell block is not supplied with the voltage through the plurality of the global word lines GWL0 to GWLn-1 because the path transistors 230 are turned off. Thus, the word lines WL0 to WLn-1 stay floated.
Meanwhile, the path transistors 230 serve as a switch for applying a predetermined voltage to the word lines WL0-to WLn-1 of the cell block 100 through the global word lines GWL0 to GWLn-1. The path transistors 230 include a high voltage transistor for drain select 250, a high voltage transistor for source select 270 and a high voltage transistor for cell select 260.
In the above construction, the block switches for driving the path transistors generate a voltage higher than the high voltage received through the global word lines, in order to stably transfer the high voltage to cells of a selected block without a threshold voltage drop.
For this, an existing block switch generates a high voltage, like a charge pump using a clock. In a low power supply voltage of below 1.8V, however, the block switch has a problem that it cannot generate a high voltage of over 18V, which is a program bias.
In order to overcome this problem, there was proposed a block switch using a precharge and self-boosting mode as shown in FIG. 2. FIG. 2 is a circuit diagram showing the configuration of a conventional block switch. FIG. 3 is a diagram showing an operational waveform of the conventional block switch. A conventional method of driving the block switch of the precharge and self-boosting mode will be described with reference to FIGS. 2 and 3.
If a select signal SELb is enabled to be a Low level and a precharge signal PREb is enabled to a Low level, first and second control signals GA and GB rise up to a pumping voltage (Vpp). In this time, a NAND gate 301, which receive the select signal SELb of the Low level and the precharge signal PREb of the Low level as an input, outputs a signal of a High level. The output signal of the High level of the NAND gate 301 is inverted to a Low level through an inverter 302, thus turning off an NMOS transistor 306. Meanwhile, NMOS transistors 303 and 304 are respectively turned on by the first and second control signals GA and GB of the pumping voltage (Vpp) level. Accordingly, the output terminal Bsel is precharged with a first voltage (Vpp−Vt) in which the threshold voltage (Vt) of the NMOS transistor 303 is subtracted from the pumping voltage (Vpp). If the precharge operation is completed and the precharge signal PREb becomes a High level, the first and second control signals GA and GB become a Low level to turn off the NMOS transistors 303 and 304, so that the output terminal Bsel[k] is floated. In this time, if a predetermined voltage is applied to the drain terminal of the path transistor through the global word lines GWL, the output terminal Bsel of the block switch is self-boosted by overlap capacitance between the drain and gate-terminals of the path transistor 307. Accordingly, the output terminal Bsel of the block switch has a voltage ΔV, which is higher than the first voltage (Vpp−Vt).
The greater the number of the path transistors 307 and the higher the voltage applied through the global word lines GWL, the more the self-boosting operation is easily generated. It is required that the boosting level, i.e., ΔV is 2Vt or more. The output terminal Bsel is increased from the first voltage (Vpp−Vt) to the second voltage (Vpp+Vt) by the self-boosting operation.
The block switch of the precharge and self-boosting mode can operate regardless of the power supply voltage. However, the operating speed of the block switch becomes slow because the precharge operation is needed before the voltage is applied to the word lines. Furthermore, in order to selectively precharge block word lines of a selected block, the first and second control signals GA and GB must be selectively applied. Thus, a decoder for applying the first and second control signals GA and GB is additionally required. In addition, since the first and second control signals GA and GB must be applied as the pumping voltage (Vpp) level, a decoder for high voltage is necessary. However, this decoder for high voltage is constructed using a switch for high voltage. Accordingly, the chip area is increased because the area of the switch is significantly great.